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u2801b preliminary information rev. a1, 19-may-99 1 (24) dect single-chip transceiver description the u2801b is an rf ic for low-power dect applica- tions. the tqfp48-packaged ic is a complete transceiver including image rejection mixer, if amplifier, fm demodulator, baseband filter, rssi, tx preamplifier, power-ramping generator for power amplifiers, inte- grated synthesizer, fully integrated vco, tx filter and modulation compensation circuit for advanced closed- loop modulation concept. no mechanical tuning is necessary in production. features supply-voltage range 3 v to 5 v (unregulated) auxiliary-voltage regulator on-chip low current consumption few low cost external components no mechanical tuning required non-blindslot and blindslot operation unlimited multislot operation with advanced closed- loop modulation (13.824 mhz/ 27.648 mhz) tx preamplifier with 0 dbm output power at 1.9 ghz and ramp-signal generator for sige power amplifier block diagram pc rc gf mcc cp vco f : n f : n ctrl logic pd tx / rx switch ir mixer if amp 1 if amp 2 demod bb filter 3-wire bus d/a rssi latch tx driver data_hold clock data enable rx_on tx_on pu_rx/tx pu_pll tx_data rssi bb_out bb_ in cf demod_ tank out if_tank if_in mixer out rf_in tx_out vs_vco cp ld ref_clk vtune vreg vs_reg reg_ctrl vreg_vco vco reg ramp gen ramp_out ramp_set aux reg pu_vco pu_reg gnd_vco 14227 figure 1. block diagram ordering information extended type number package remarks U2801B-MFY tqfp48 tray U2801B-MFYg3 tqfp48 taped and reeled
u2801b rev. a1, 19-may-99 preliminary information 2 (24) pin description clock data enable ref_clk ld pu_reg vs_pll vreg reg_ctrl vs_reg gnd_cp vs_cp ramp_out if_in2 if_in1 vs_if tx_out gnd3 rf_in2 rf_in1 gnd2 if_tank2 if_tank1 rssi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 u2801b rx_on tx_on mixer_out1 pu_vco tx_data vs_mixer gnd_pll pu_rx/tx pu_pull data_hold ramp_set mixer_out2 cp gnd_vco vs_vco gnd1 vtune vreg_vco bb_out bb_in bb_cf demod_out demod_tank2 demod_tank1 14228 figure 2. pinning pin symbol function configuration 1 clock 3-wire-bus: clock input 2 data 3-wire-bus: data input 3 enable 3-wire-bus: enable input
u2801b preliminary information rev. a1, 19-may-99 3 (24) pin description (continued) pin symbol function configuration 4 ref_clk reference-frequency input 5 ld lock-detect output 6 pu_reg aux. voltage regulator power-up input 7 vs_pll pll supply voltage
u2801b rev. a1, 19-may-99 preliminary information 4 (24) pin description (continued) pin symbol function configuration 8 vreg aux. voltage-regulator output 9 reg_ctrl aux. voltage-regulator control output 10 vs_reg aux. voltage-regulator supply voltage 11 gnd_cp charge-pump ground 12 vs_cp charge-pump supply voltage 13 cp charge-pump output 14 vs_vco vco voltage-regulator supply voltage 15 vreg_vco vco voltage-regulator control output 16 gnd_vco vco ground 17 vtune vco tuning voltage input
u2801b preliminary information rev. a1, 19-may-99 5 (24) pin description (continued) pin symbol function configuration 18 gnd1 ground 19 demod_tank1 demodulator tank circuit 20 demod_tank2 demodulator tank circuit 21 demod_out demodulator output
u2801b rev. a1, 19-may-99 preliminary information 6 (24) pin description (continued) pin symbol function configuration 22 bb_in baseband filter input 23 bb_cf baseband filter corner-frequency control input 24 bb_out baseband filter output 25 rssi received signal-strength indicator output 26 if_tank1 if tank circuit 27 if_tank2 if tank circuit
u2801b preliminary information rev. a1, 19-may-99 7 (24) pin description (continued) pin symbol function configuration 28 gnd2 ground 29 rf_in1 differential rf input of image reject mixer 30 rf_in2 differential rf input of image reject mixer 31 gnd3 ground
u2801b rev. a1, 19-may-99 preliminary information 8 (24) pin description (continued) pin symbol function configuration 32 tx_out tx driver amplifier output for pa 33 vs_if if amplifier supply voltage 34 if_in1 differential if input of if amplifier 35 if_in2 differential if input of if amplifier
u2801b preliminary information rev. a1, 19-may-99 9 (24) pin description (continued) pin symbol function configuration 36 ramp_out ramp-generator output for pa power ramping 37 ramp_set slew-rate setting of ramping signal 38 rx_on rx control input 39 tx_on tx control input 40 mixer_out1 differential mixer output for saw filter 41 mixer_out2 differential mixer output for saw filter
u2801b rev. a1, 19-may-99 preliminary information 10 (24) pin description (continued) pin symbol function configuration 42 vs_mixer mixer supply voltage 43 gnd_pll pll ground 44 pu_vco vco power-up input 45 pu_rx/tx rx/tx power-up input 46 pu_pll pll power-up input
u2801b preliminary information rev. a1, 19-may-99 11 (24) pin description (continued) pin symbol function configuration 47 tx_data tx data input of gaussian filter and modulation-compensation circuit 48 data_hold data-hold input to keep the latch information in power-down mode functional description receiver the rf-input signal at rf_in is fed to an image rejection mixer ir_mixer with its differential outputs mixer_out1 and mixer_out2 driving an if saw filter at 110.592 mhz or 112.320 mhz. if amplifier if_amp1 and if_amp2 with external if_tank and in- tegrated rssi function feed the signal to the demodulator demod and finally to an integrated baseband filter bb. for demodulator tuning in production an integrated 5-bit digital to analog converter d/a is used to control the on- chip varicap diode. transmitter the transmit data at tx_data is filtered by an integrated gaussian filter gf and fed to the fully integrated vco op- erating at twice the output frequency. after modulation the signal is frequency divided by 2 and fed via a tx/rx switch to the tx_driver. this driver amplifier sup- plies 0 dbm output power at tx_out. a ramp signal generator ramp_gen, providing ramp-signals at ramp_out for use with the u7004b or u7006b sige power amplifier, is also integrated. the slope of the ramp signal is controlled by a capacitor at ramp_set. synthesizer the ir_mixer, the tx_driver and the programmable counter pc are driven from the fully integrated vco (including on chip inductors and varactors). for preset of vco frequency an integrated 3-bit digital-to-analog converter is used. the output signal is divided in frequency to supply the desired frequency to the tx_driver, 0/90 degree phase shifter for the ir_mixer and to be used by the pc for the phase detector pd. operating with reference clock frequencies of 13.824 mhz and 27.648 mhz supplied to the reference counter rc the pd and charge pump cp are operating at 3.456 mhz resulting in low settling time and thus allowing blindslot and non-blindslot operation. unlimited multislot operation is possible by use of the integrated advanced closed loop modulation concept based on the modulation compensation circuit mcc. power supply for minimum interference and maximum signal isolation an integrated bandgap-stabilized voltage regulator for use with an external low-cost pnp transistor is implemented. additionally three independent internal voltage regula- tors provide multiple power down and current saving modi.
u2801b rev. a1, 19-may-99 preliminary information 12 (24) pll principle rf_in programable counter pc o main counter mc o swallow counter sc f vco = f pd x (s mc x 32 + s sc ) f vco f pd phase frequency cp divider pa driver detector pd vco mixer dac f pd = 3.456 mhz gf_data controlled phase shifting modulation gaussian compensation mcc filter gf reference counter rc 13.824 mhz ref_clk s rc 13.824mhz 4 (20.736mhz)* 6 27.648mhz 8 * mcc and gf not possible 1.152 mbit/s pll reference tx_data frequency ref_clk baseband controller figure 3.
u2801b preliminary information rev. a1, 19-may-99 13 (24) the following table shows the lo frequencies for rx and tx for the dect band plus additional channels for an optional dect band extension. intermediate frequencies of 110.592 and 112.32 mhz are supported. table 1. lo frequencies mode f if /mhz channel f ant /mhz f vco /mhz f vco /2/mhz s mc s sc tx c0 1897.344 3794.688 1897.344 34 10 c1 1895.616 3791.232 1895.616 34 9 c2 1893.888 3787.776 1893.888 34 8 c3 1892.160 3784.320 1892.160 34 7 c4 1890.432 3780.864 1890.432 34 6 c5 1888.704 3777.408 1888.704 34 5 c6 1886.976 3773.952 1886.976 34 4 c7 1885.248 3770.496 1885.248 34 3 c8 1883.520 3767.040 1883.520 34 2 c9 1881.792 3763.584 1881.792 34 1 rx 110.592 c0 1897.344 3573.504 1786.752 32 10 c1 1895.616 3570.048 1785.024 32 9 c2 1893.888 3566.592 1783.296 32 8 c3 1892.160 3563.136 1781.568 32 7 c4 1890.432 3559.680 1779.840 32 6 c5 1888.704 3556.224 1778.112 32 5 c6 1886.976 3552.768 1776.384 32 4 c7 1885.248 3549.312 1774.656 32 3 c8 1883.520 3545.856 1772.928 32 2 c9 1881.792 3542.400 1771.200 32 1 112.32 c0 1897.344 3570.048 1785.024 32 9 c1 1895.616 3566.592 1783.296 32 8 c2 1893.888 3563.136 1781.568 32 7 c3 1892.160 3559.680 1779.840 32 6 c4 1890.432 3556.224 1778.112 32 5 c5 1888.704 3552.768 1776.384 32 4 c6 1886.976 3549.312 1774.656 32 3 c7 1885.248 3545.856 1772.928 32 2 c8 1883.520 3542.400 1771.200 32 1 c9 1881.792 3538.944 1769.472 32 0 table 2. limits mode f if /mhz f ant /mhz f vco /mhz f vco /2/mhz s mc s sc tx fmin 1769.472 3538.944 1769.472 32 0 rx 110.592 1880.064 3538.944 1769.472 32 0 112.320 1826.496 3538.944 1769.472 32 0 tx fmax 1988.928 3977.856 1988.928 35 31 rx 110.592 2099.520 3977.856 1988.928 35 31 112.320 2101.248 3977.856 1988.928 35 31 formula f ant ci f ant ci1 = 1.728 mhz for tx: f vco = 2 x f ant for rx: f vco = 2 x (f ant f if )
u2801b rev. a1, 19-may-99 preliminary information 14 (24) control signals ld output, which is active after pll is locked and test-mode output (according to programmed test mode) pu_reg hardware power up > standby of regulator pu_vco hardware power up > standby of voltage controlled oscillator pu_rx/tx hardware power up > standby of rx/ tx part pu_pll hardware power up > standby of synthesizer table 3. logic standby standby hold register tx mode rx mode rssi only data_hold 0 1 x x x pu_reg 0 0 1 1 1 pu_vco x x 1 1 1 pu_rx/tx x x 1 1 1 pu_pll x x 1 1 1 rx_on x x 0 1 1 tx_on x x 1 0 1 bb filter off off off on off demodulator off off off on off if amplifiers and rssi off off off on on ir mixer off off off on on rx switch off off on on on tx switch off off on off off tx driver off off on off off ramp generator off off on off off programmable counter off off on on on voltage-controlled oscillator off off on on on gaussian filter off off on off off phase detector / charge pump off off on on on modulation compensation circuit off off on off off reference counter off off on on on current consumption / ma @ v s = 3.2 v <0.01 <0.1 54 85 80 serial programming bus reference and programmable counters can be programmed by the 3-wire bus (clock, data and enable). besides this information additional control bits as phase detector polarity and scaling of charge-pump currents as well as internal currents for gaussian lowpass filter and modulation compensation circuit can be transferred. after setting enable signal to low condition, on the rising edge of the clock signal, the data status is transferred bit by bit into the shift register, starting with the msb-bit. after enable returning to high condition the programmed information is loaded into the addressed latches, according to the addressbit condition (last bit). additional leading bits are ignored and there is no check made how many pulses have arrived during enable-low condition. the bus then returns to a low current standby mode until the enable signal changes to low again. to keep the information in the registers of the pll during standby data_hold must be set to high condition.
u2801b preliminary information rev. a1, 19-may-99 15 (24) bus protocol formats msb lsb data bits address bit d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a0 rc sc mc ps gf mcc gfcs vcodac cpcs 1 1 0 0 1 1 1 1 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 standard bit setting: word 1 e10 e9 e8 e7 e6 e5 e4 e3 e2 e1 e0 a0 demoddac mccs test 0 word 2 0 0 0 0 0 0 0 0 0 0 0 0 pll settings rc (reference divider) d22 d21 s rc 0 0 0 1 4 1 0 6 1 1 8 mc (main divider) d15 d14 s ms 0 0 32 0 1 33 1 0 34 1 1 35 sc (swallow counter) d20 d19 d18 d17 d16 s sc 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 ... ... 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 phase settings phase of gf-output (internal connection) d13 gf-data 0 source 1 sink phase of mcc-output (internal connection) d12 mcc-data 0 inverted 1 normal phase of cp (charge pump) d11 f r > f p f r < f p f r = f p 0 i sink i source high imp. 1 i source i sink high imp. current savings power up/down settings d10 gf (gaussian filter) 0 off 1 on d9 mcc (modulation compensation circuit) 0 off 1 on
u2801b rev. a1, 19-may-99 preliminary information 16 (24) current gain settings gfcs (gaussian filtered current settings) d8 d7 d6 gfcs 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% cpcs (charge-pump current settings) (internal connection) d2 d1 d0 cpcs 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% mccs (modulation compensation current settings) (internal connection) e5 e4 e3 mccs 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% pretune dac voltage settings pretune dac voltage (internal connection) d5 d4 d3 f vco /% 0 0 0 12.0 0 0 1 ... 0 1 0 ... 0 1 1 ... 1 0 0 ... 1 0 1 ... 1 1 0 ... 1 1 1 12.0 test mode settings test output pin (lock detect) d11 e2 e1 e0 signal at lock detect output cp mode x 0 0 0 lock detect active 0 0 0 1 rc out active 1 0 1 0 pc out active x 0 1 1 rc out divided by 2048 (mcctest) active x 1 0 0 cp tristate only high imp. 0 1 0 1 rc out high imp. 1 1 1 0 pc out high imp. x 1 1 1 rc out divided by 2 (gftest) high imp. demod dac voltage settings (demoddac) demod dac voltage (internal connection) e10 e9 e8 e7 e6 f ifcenter % 0 0 0 0 0 6.0 0 0 0 0 1 ... 0 0 0 1 0 ... ... 1 1 1 0 1 ... 1 1 1 1 0 ... 1 1 1 1 1 6.0
u2801b preliminary information rev. a1, 19-may-99 17 (24) 3-wire bus protocol timing diagram data clock enable tt tec ts tc th tl tper 16525 figure 4. description symbol min. value unit clock period tper 125 ns set time data to clock ts 60 ns hold time data to clock th 60 ns clock pulse width tc 125 ns set time enable to clock tl 200 ns hold time enable to data tec 0 ns time between two protocols tt 250 ns absolute maximum ratings all voltages are referred to gnd parameter symbol min. max. unit supply voltage regulator pin 10 v s_reg 3.2 *) 6.0 v supply voltage pins 7, 12, 14, 33 and 42 v s 3.0 6.0 v logic input voltage pins 1, 2, 3, 38, 39, 44, 45, 46, 47 and 48 v in 0.3 v s v junction temperature t jmax 150 c storage temperature t stg 40 150 c thermal resistance parameters symbol value unit junction ambient r thja t.b.d. k/w operating range parameter symbol min. typ. max. unit supply voltage regulator pins 10 v s 3.2 *) 3.2 *) 5.5 v supply voltage pins 7, 12, 14, 33 and 42 v s 3.0 3.0 5.5 v ambient temperature t amb 25 +25 +85 c *) optionally 3.0 v, if not using the voltage regulator
u2801b rev. a1, 19-may-99 preliminary information 18 (24) electrical characteristics test conditions (unless otherwise specified): v s_reg = 3.2 v, t amb = 25 c parameters test conditions / pins symbol min. typ. max. unit receiver ir mixer pins 29, 30, 40 and 41 input impedance pins 29 and 30 z in 50 w input matching pins 29 and 30 vswr in <2:1 image rejection ratio pins 40 and 41 irr 20 db dsb noise figure pins 40 and 41 nfdsb= nfssb 10 db conversion gain r load = 200 w g conv 12 db output interception point pins 40 and 41 oip3 10 dbm if amplifier pins 26, 27, 34 and 35 input impedance pins 34 and 35 z in 200 400 w lower cut-off frequency fl 3db 90 mhz upper cut-off frequency fu 3db 130 mhz power gain gp 85 db bandwidth of external tank cir- cuit pins 26 and 27 bw3db 10 mhz noise figure nf 9 db rssi pins 25, 34 and 35 rssi sensitivity at if_in1, if_in2 pins 34 and 35 p min 20 db m v rssi compression at if_in1, if_in2 pins 34 and 35 p max 100 db m v rssi dynamic range dr 80 db rssi resolution slope of the rssi has to be steady acc 2 db rssi rise time p in = 30 to 100 db m v, pin 25 t r 1 m s rssi fall time p in = 100 to 30 db m v, pin 25 t f 1 m s quiescent output current @ p in < 20 db m v at if_in1, if_in2 pin 25 i out 30 m a maximum output current @ p in = 100 db m v at if_in1, if_in2 pin 25 i out 150 m a fm demodulator pins 19, 20 and 21 co-channel rejection ratio @ p in = 75 dbm at ir-mixer input ccrr 10 db sensitivity quality factor of external tank circuit approx. 20, pin 21 s 0.5 v/mhz amplitude of recovered signal nominal deviation of signal 288 khz, pin 21 a 288 mvss output voltage dc range pin 21 fm outdc 0.4 vs0.4 v output impedance pin 21 z out 13 k w am rejection ratio pin 21 amrr t.b.d. db dac for fm demodulator (internally connected) (5-bit programming see bus protocol e5 to e10) dac range t dac 6 %
u2801b preliminary information rev. a1, 19-may-99 19 (24) electrical characteristics (continued) parameters test conditions / pins symbol min. typ. max. unit transmitter/ pll vco frequency range f vco 3500 4000 mhz tuning gain pin 17 g tune 150 mhz/v frequency control voltage range pin 17 v tune 0.4 2.3 v dac for vco pretune (internally connected) (3-bit bus programming se bus protocol d3 to d5) dac tuning range d f vco,dac 5 % pll pin 4 scaling factor prescaler s psc 32 / 33 scaling factor main counter s mc 32 / 33 / 34 / 35 scaling factor swallow counter s sc 0 31 external reference input frequency ac coupled sinewave pin 4 f ref_clk 13.824 27.648 mhz mhz external reference input voltage ac coupled sinewave pin 4 v ref_clk 50 250 mv rms scaling factor reference counter s rc 4 / 6 / 8 charge pump (active when rx, tx) pin 13 output current v i_cp_sw = `0', v cp = v vs_cp / 2 i cp_1 1 ma current scaling factor i cp = cpcs * i cp_typ (see bus protocol d0 ... d2) cpcs 60 130 % leakage current i l 100 pa gaussian transmit filter (gaussian shape b * t = 0.5) f ref_clk has to be chosen ! tx data filter clock f ref_clk = 13.824 mhz, tx, 18 taps in filter, s rc = 12 f txfclk 13.824 mhz f ref_clk = 27.648 mhz, tx, 18 taps in filter, s rc = 24 f txfclk 13.824 mhz frequency deviation polarity (see bus protocol d13) gf fm_typ 576 khz frequency deviation scal- ing gf fm = gf fm_typ * gfcs (see bus protocol d6 ... d8) gfcs 60 130 % modulation compensation circuit @ maximum dsv 64 (internally connected) oversampling f ref_clk = 13.824 mhz or = 27.648 mhz ovs 9 integration counter mac 576 576 current scaling factor (see bus protocol e3 ... e5) mccs 60 130 %
u2801b rev. a1, 19-may-99 preliminary information 20 (24) electrical characteristics (continued) parameters test conditions / pins symbol min. typ. max. unit vco switch and tx driver pin 32 power gain @ p in = 40 dbm gp 30 db output impedance pin 3 2 z out 100 w maximum output power pin 3 2 p max 3 dbm gain compression @ tx_rf_out pin 3 2 p 1db 1 dbm output interception point pin 3 2 oip3 10 dbm ramp generator pins 36 and 37 minimum output voltage accordind to ramp_set input v min 0.2 v maximum output voltage according to ramp_set input v max 1.95 v rise time c ramp = 270 pf at pin 37 t r 5 m s fall time c ramp = 270 pf at pin 37 t f 5 m s lock detect and test mode output pin 5 lock detect output, test mode output locked = `1' unlocked = `0' test modes (see bus proto- col e0 ... e2) ld leakage current v oh = 5.5 v i l 5 m a saturation voltage i ol = 0.5 ma v sl 0.4 v auxiliary regulator pins 8, 9 and 10 output voltage pin 8 v reg 2.9 3.0 3.1 v supply voltage rejection v pin10 = v dc + 0.1 v pp f pin10 = 0.1 to 10 khz c pin8 = 100 nf svr tbd db auxiliary regulator pins 14, 15 and 16 output voltage pin 15 v reg_vco 2.6 2.7 2.8 v 3-wire bus clock f clock 1.152 6.912 mhz
u2801b preliminary information rev. a1, 19-may-99 21 (24) electrical characteristics (continued) parameters test conditions / pins symbol min. typ. max. unit logic input levels (clock, data, enable, rx_on, tx_on, pu_vco, tx_data, data_hold) pins 1, 2, 3, 38, 39, 44, 47 and 48 high input level = `1' v ih 1.5 v low input level = `0' v il 0.5 v high input current = `1' i ih 5 5 m a low input current = `0' i il 5 5 m a standby control pins 6, 45 and 46 power up pu_reg = `1` pu_rx/tx = `1` pu_pll = `1` high input level pin 6 pin 45 pin 46 v pu_reg v pu_rx/tx v pu_pll 2.0 v standby pu_reg = `0` pu_rx/tx = `0` pu_pll = `0` low input level pin 6 pin 45 pin 46 v pu_reg,off v pu_rx/tx,off v pu_pll,off 0.7 v power up pu_reg = `1` pu_rx/tx = `1` pu_pll = `1` high input current v pu = 3 v pin 6 v pu = 5.5 v pin 45 v pu = 3 v pin 46 v pu = 5.5 v i pu_reg i pu_rx/tx i pu_pll 20 60 100 200 30 80 125 300 40 100 150 400 m a m a m a m a standby pu_xxxx = `0' low input current v pu = 0 v pin 6, v pu = 0.5 v pins 45, 46 i pu,off 0.1 1 m a m a settling time v s = 0 active operation switched from v s = 0 to v s = 3v t soa < 10 m s settling time standby active operation switched from pu = `0' to pu = `1' t ssa < 10 m s settling time active operation standby switched from pu = `1' to standby t sas < 2 m s power supply pins 7, 10, 12, 14, 33 and 42 total supply current rx i s 85 ma rssi only i s 82 ma tx i s 54 ma tx (mcc, gf active) i s 58 ma standby current, mode 1 pu_rx/tx = gnd i s 1 10 m a mode 2 pu = gnd, data_hold = v s i s 50 100 m a supply current cp v vs_cp = 3 v, pll in lock condition pin 13 i cp 1 m a
u2801b rev. a1, 19-may-99 preliminary information 22 (24) typical application circuit 14229 figure 5. typical application circuit
u2801b preliminary information rev. a1, 19-may-99 23 (24) package information 13053 package pqfp48 dimensions in mm
u2801b rev. a1, 19-may-99 preliminary information 24 (24) ozone depleting substances policy statement it is the policy of temic semiconductor gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( odss). the montreal protocol ( 1987) and its london amendments ( 1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. temic semiconductor gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2 . class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency ( epa ) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c ( transitional substances ) respectively. temic semiconductor gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. we reserve the right to make changes to improve technical design and may do so without further notice . parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use temic semiconductors products for any unintended or unauthorized application, the buyer shall indemnify temic semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. temic semiconductor gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 ( 0 ) 7131 67 2594, fax number: 49 ( 0 ) 7131 67 2423

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